The present technology relates to a solid-state imaging device and a camera system which device has a layered structure consisted of two chips and is formed by dividing a wafer into pieces due to dicing.
Typically, an image capturing device is obtained by assembling individual packages, as modules, in which two chips of a CMOS image sensor (CIS) chip and an image processing chip are mounted, respectively.
Or, there is also a case of each of the chips undergoing COB (Chip On Board) packaging.
In case of an image capturing device mounted in a mobile phone or the like, reduction in packaging area and miniaturization are expected recent years, and thus, SOC (System On Chip) technology for integrating the above-mentioned two chips into one chip is developed.
However, process for the integration into one chip in which process CIS process and hi-speed logic process are mixed expects increased steps and costs high, and in addition, is difficult to manage both analog characteristics and logic characteristics, this leading to the risk of deterioration of characteristics of the image capturing device.
Therefore, a method for managing both miniaturization and improvement in characteristics due to a layered structure obtained by chip-level assembling of the above-mentioned two chips is proposed (see, Japanese Patent Laid-Open No. 2004-146816 and Japanese Patent Laid-Open No. 2008-085755).
Portions (A) and (B) of FIG. 1 illustrate a process flow of a solid-state imaging device with a layered structure.
As illustrated in portion (A) of FIG. 1, after wafers 1 and 2 prepared with processes most suitable for respective upper and lower first and second chips are pasted together, the rear face of the upper chip is polished and the thickness of the wafer of the upper chip is made thinner.
Signal lines and power supply lines between the upper and lower chips are electrically joined through via holes (TCV: Through Chip Via) whose through holes are filled with metal.
Then, as illustrated in portion (B) of FIG. 1, after performing processing to obtain color filters and microlenses on the first chip (upper chip) side, chips are cut out by dicing.
FIG. 2 is a diagram for explaining a typical method of cutting out chips by dicing. Moreover, CW in FIG. 2 denotes a cutting width with a blade.
The wafer with the layered structure in which chips CP are arranged in an array shape is cut with a blade along scribe lines SCL indicating positions for cutting between the chips, and is divided into the individual chips CP.
In FIG. 2, a simplified cross section taken along the scribe line SCL which is the position for cutting is partially enlarged and illustrated.
In the layered structure in FIG. 2, a silicon (Si) layer 11 and a nitride film (for example, SiN film) 12 are layered to form the CIS-side wafer 1. In practice, sensors and the like are formed on the other face side opposite to the face of the Si layer 11 on which the SiN film is formed.
A silicon layer 21, an oxide film 22, a wiring (for example, copper) layer 23, an SiO2 layer 24 and an SiO2 layer 25 are layered to form the logic-side wafer 2.
Furthermore, in the simplified structure in FIG. 2, the SiN film 12 of the CIS-side wafer 1 and the SiO2 layer 25 of the logic-side wafer 2 are pasted together.
Furthermore, in the CIS-side wafer 1 and logic-side wafer 2, guard rings GDR1 and GDR2 for preventing cracks from propagating to the chip side, and the like, are formed in regions of the scribe lines SCL which regions are near the chips.
Dicing includes blade dicing after laser ablation, stealth dicing, and the like other than the above-mentioned blade dicing solely with a blade.